1. Field of the Invention
The invention pertains generally to computer data buses. In particular, it pertains to reducing latency on a bus by performing a data bus inversion operation in parallel with an error correction operation.
2. Description of the Related Art
Improvements in processor speed have increased the pressure to transfer data more quickly throughout the computer system. In a related effort, system designers attempt to minimize power consumption and electrical noise caused by high-speed switching on the data lines. This has led to a development described as Data Bus Inversion (DBI), which is a bus technique that examines the data bits being transmitted over the parallel lines of a data bus, determines the number of bits that are active (meaning the line is being driven by an active transistor output rather than being passively held at a predetermined voltage level by an inactive output), and inverts the data bits if more than half of them are active, thereby resulting in less than half of them being active on the bus. This minimizes the number of line driver transistors that are active during any given data transfer, resulting in a reduction in power consumption and a reduction of the other problems that are caused by multiple high speed lines being turned on at the same time.
FIG. 1 shows an example of a system 1 using DBI. A bus requester 10 (a device that can initiate a transfer over the bus) makes a request to write to memory 11 over data bus 18, which may have multiple parallel data lines. A diagonal slash across a connecting line in the figures indicates multiple parallel lines (for example, 16 or 32 lines) that are illustrated as a single line for simplicity.
Requestor 10 can be a processor or any other device capable of initiating a read or write operation to memory. The data lines from requestor 10 go to inverter 16, where they may or may not be inverted before being placed on bus 18. The data lines are also monitored by inversion decision logic 14. In the case of a write operation, the data from device 10 is examined by decision logic 14 to determine if more than half the data lines are active. If they are, decision logic 14 sends a signal to inverter 16 to invert the data lines before placing them on bus 18. If fewer than half of the data lines are not active, the signal from logic 14 to inverter 16 indicates that no inversion is necessary, and inverter 16 allows the data signals to pass to bus 18 without inversion.
If the data has been inverted, the receiving circuitry must invert it again to restore the original data. If the data has not been inverted, the receiving circuit leaves the data as it is. Since the receiving circuit must know which to do, a status line 19 is incorporated in the bus to indicate whether the data is inverted. If inversion decision logic 15 receives an indication of inversion over line 19, it sends a signal to inverter 17 to invert the data back to its original form before passing the data on to memory 11.
The system can also work in the opposite direction for data being read from memory, with decision logic 15 deciding whether to invert the data, and sending a signal on status line 19 telling decision logic 14 whether to reinvert the data before passing the data to requester 10.
While inverting the data is simple and fast, deciding whether to invert the data involves a time-consuming process of counting the active bits. This time is added to the amount of time it takes to complete a data transfer. This increase in latency, while small in absolute terms, can be a significant fraction of bus transfer time when dealing with high-speed data buses capable of transferring data in nanoseconds. An increase of 10-20% in bus latency can reduce bus bandwidth by a comparable amount, resulting in a significant loss of system performance.
The bus latency problem is further aggravated by the operation of error correction code circuitry, as shown in system 2 of FIG. 2. RAM memory is commonly subject to data errors. To counteract this, most modern memory systems incorporate error correction code (ECC) logic. When write data is received, ECC logic 23 generates a multi-bit code based on the particular bit pattern in the data, and stores that code in memory with the associated data. When the data is later read from memory, the ECC code is calculated again using the same algorithm, based on the data just read from memory 21. If the old and new codes match, the data is considered correct and is handled normally. However, if the two codes disagree, ECC logic 23 assumes an error in the data from memory, so it corrects the error based on the ECC code retrieved from memory. ECC algorithms permit most errors to be corrected in this manner, thus allowing the data to be forwarded and processing to continue. Unfortunately, generating and comparing the ECC code also takes a finite amount of time, which is added to the total time for the data transfer. If an error occurs and the data has to be corrected, the additional time delay is even greater.
The benefits of ECC data correction are generally considered to outweigh the resultant increase in bus latency. However, when the delay caused by DBI is added to the delay caused by ECC, the total latency in a bus transaction may become intolerable.